Power consumption is an important consideration in wireless sensor network application. In order to extend the use time of the applications, low-power system chip with lower power consumption is required. In a system chip, static random access memory consumes the majority of the power consumption. Therefore, in order to reduce the power consumption of a static random access memory, some technologies such as modulating the voltage scaling to near-threshold voltage or sub-threshold voltage have been developed.
Conventional, the characteristics of a memory may vary with the advanced manufacturing process and the reduction of source voltage (VDD). For example, when the source voltage is reduced, the signal level of a related signal as well as the noise margin is consequently reduced. Once the noise margin is smaller than a safe value (for example, 0), the memory may not work normally. In general, a memory may be operated in a read mode, a write mode or a hold mode. In the read mode, the memory has the smallest noise margin; in the hold mode, the memory has the largest noise margin; and in the write mode, the memory has a noise margin in between. In addition, when the memory performs a data writing operation, the unselected memory cell in a memory matrix may be affected by a noise and is in a pseudo read mode; and therefore, the stored data may have errors.
In order to solve the issue of a memory in read mode having the smallest noise margin, a circuit design of memory is provided by using 8T memory unit with separated read and write functions. Because the transistors for read function are separated, the noise margin in the read mode is increased as large as the noise margin in the hold mode. However, the circuit design by separating the transistors for read function and write function may need extra two transistors. Thus, compared with the 6T memory unit, the 8T memory unit requires extra 40% of circuit area and still cannot solve the pseudo read issue.
Another circuit design is provided to solve the issues of the read mode having the smallest noise margin and the pseudo read. In this circuit design, the feature of read prior to write is adopted besides of the feature of read and writes separation. Further, the pseudo read issue may be also solved by a circuit design by dividing the word lines into horizontal word lines and vertical word lines. However, the aforementioned two circuit designs may require extra transistors (such as 8T, 10T, 12T or even more) and extra power consumption.
In order to solve the issues of the read mode having the smallest noise margin and the pseudo read without employing extra transistors, a circuit design is provided by employing 6T memory unit with hierarchical bit-line design. It is to known that the noise margin in read mode increases with the decrement of the number of memory unit on the bit line due to that the fewer number of the memory unit may result in the faster the rate of discharge and the shorter the time memory unit affected by noise. However, the number of the memory unit on bit line, the noise margin and the circuit area of the memory matrix the three must be properly adjusted. For example, if the smaller circuit area of a memory matrix is desired, the number of the memory unit on bit line must be reduced and consequently a reduced noise is resulted.
Therefore, it is quite important to provide a memory having advantages such as having a large noise margin in read and pseudo read modes, capable of operating under an ultra-low voltage and having lower power consumption but without having to sacrifice area density of the memory matrix.